The present invention relates to thin-film structures.
Whetten, U.S. Pat. No. 5,062,690, describes a liquid crystal display with scan lines and data lines. Col. 2 lines 5-27 describe how short circuits between data lines and scan lines are sources of defects and how scan and data lines are insulated from each other at their crossover locations by a thin layer of an insulation material, such as silicon nitride (SiN). The data and scan lines can short to one another at the crossover locations through holes that may inadvertently develop in the insulation layer during device fabrication. Typically, metallization for the data and scan lines is deposited by sputtering during different process steps, so that the later deposited metallization will be deposited through any holes or openings in the insulation layer formed in contact with the first deposited metallization. As shown and described in relation to FIG. 2, scan lines and data lines are electrically isolated by a layer of insulation, preferably SiN; since the process steps of field-effect transistors (FETs) require a "sandwich" structure of SiN, amorphous silicon (a-Si) and doped a-Si, a layer of a-Si and a layer of doped a-Si may also be deposited between the scan and data lines. Col. 5 lines 11-33 describe deposition of a layer of hydrogenated silicon nitride, a layer of hydrogenated amorphous silicon, and a heavily doped layer of hydrogenated amorphous silicon, which can be an N+ layer.
As shown and described in relation to FIGS. 6A-9B, each scan and data line crossover location can have a redundant crossover with an open circuit that may be closed by a laser-fusible link to create a shunt around the crossover location if the scan and data lines are shorted. The crossover location may be electrically isolated by severing the scan line and data line at locations between points where the redundant crossovers connect. Col. 8 lines 9-17 mentions that metallization thicker than 200 angstroms could be used, but then there is a risk of step coverage problems when subsequent layers of materials are deposited over the first metallization pattern.
Col. 8 lines 38-46 mentions that the insulation layer may be about 500-1500 angstroms thick, with a thicker layer increasing voltage required to turn on FETs and a thinner layer increasing probability of defects within FETs or between scan and data lines at crossovers. Patterns of the insulation layer of SiN and layers of a-Si on it are shown and described in relation to FIG. 7B.